RDIMM vs LRDIMM: Populating Server Memory Correctly

Two servers with the same processor and the same total memory capacity can differ substantially in memory bandwidth, and the reason is almost always module selection and slot placement. RDIMM versus LRDIMM is part of that decision, but it is usually a smaller factor than how many channels you fill. Here is what each module type does electrically, and the population rules that follow from it.

What the register and the buffer actually do

An unbuffered DIMM (UDIMM) wires the memory controller directly to every DRAM device on the module. That is workable for one or two modules in a desktop, but the electrical load of many DRAM devices sitting on a shared command and address bus caps both capacity and clock speed.

A registered DIMM (RDIMM) inserts a register — a clock, command and address buffer — between the controller and the DRAM devices. The controller now drives one load per module on those signals instead of one load per DRAM chip. The data lines (DQ and DQS) still run straight to the DRAM devices, so data-bus loading continues to rise with every rank you add to the channel.

A load-reduced DIMM (LRDIMM) buffers the data lines as well. On DDR4 this is done with data buffers distributed across the module alongside the register, so the channel sees essentially one electrical load per module regardless of how many ranks that module carries. That is why LRDIMMs reach the highest per-module capacities on DDR4 and can hold their rated speed with more modules and more ranks installed.

Attribute	RDIMM	LRDIMM
Signals buffered	Clock, command, address	Clock, command, address and data
Load presented to the channel	Rises with rank count	Effectively one load per module
Typical DDR4 capacities	8–64 GB, up to 128 GB on 3DS parts	32–128 GB
Ranks supportable per channel	Lower	Higher, including quad-rank modules
Latency	Baseline	Slightly higher; the buffer costs cycles
Power per module	Lower	Higher, the buffer draws current
Best fit	One to two DIMMs per channel, bandwidth first	Maximum capacity per socket
Mixing	Never mix RDIMM and LRDIMM in the same system. Never mix either with UDIMM.

Ranks are the currency, not gigabytes

Memory controllers budget ranks per channel, not just modules. DDR4 platforms commonly allow up to eight logical ranks per channel, and the speed you actually achieve depends on how much load those ranks place on the data bus. On the Xeon E5-2600 v3 and v4 generation, which permits three DIMMs per channel, three dual-rank RDIMMs sit comfortably inside the rank budget and can still refuse to train at the top speed bin. Because an LRDIMM presents a single load, quad-rank modules stay usable at sensible clocks, which is what makes the largest per-socket capacities possible at all.

Stacked-die construction is a separate axis from buffering, and it is easy to conflate the two. 3DS parts stack DRAM dies behind a single load-reducing interface, and DDR4 shipped 3DS in both RDIMM and LRDIMM form — it is how the 128 GB class of module is built in either family. When you are reading a part description, check the buffering type and the 3DS designation separately.

Rank count cuts the other way for performance. A dual-rank module normally edges out a single-rank module of the same capacity and speed grade, because the controller can interleave across ranks and hide some activation overhead. Given a choice between 1Rx8 and 2Rx8 at the same capacity, take the dual-rank part.

Device width matters for reliability. Modules built from x4 DRAM devices support the stronger single-device correction modes on Intel Xeon Scalable platforms — SDDC and ADDDC — while x8 modules fall back to standard SEC-DED ECC, which still corrects single-bit errors but cannot ride out the failure of a whole DRAM device. On a machine carrying production workloads, specify x4.

Population rules that outweigh the module type

1. Fill channels before you fill slots. On an eight-channel socket, eight 32 GB modules will beat four 64 GB modules at the same 256 GB total, every time. Channel count is the multiplier on peak bandwidth; capacity per module is not.
2. Keep every channel identical. Mixed capacities or mixed rank counts across channels push the platform toward a lower common denominator and can disable or degrade interleaving.
3. Follow the slot order in the service manual. Both Dell and HPE colour-code slots and expect the white slots populated first, with the higher-rank or higher-capacity module in the slot farthest from the CPU. This is not cosmetic; it changes the termination the controller sees.
4. Expect a speed step at two DIMMs per channel. Many DDR4 platforms rate their top data rate only at one DIMM per channel and drop a bin at two — Cascade Lake's 2933 grade is a familiar example. If you are specifying for bandwidth, one DIMM per channel with larger modules often beats two smaller ones.
5. Match speed grades. The whole system runs at the slowest installed module, and at the slowest rate the CPU supports. A single leftover 2400 module will pull a 2933-capable bank down with it.

Channel counts vary more than people expect across the generations on the market. Xeon E5-2600 v3 and v4 give four channels per socket with up to three DIMMs per channel. First- and second-generation Xeon Scalable (LGA3647) give six channels with two per channel. Third-generation Ice Lake (LGA4189) and AMD EPYC 7001/7002/7003 (SP3) give eight, again at two DIMMs per channel. Working out the target capacity per channel before choosing modules avoids the common outcome of a fully populated machine running a bin or two below its rating. If you are still deciding on a platform, the refurbished server range spans all of these socket generations.

Where DDR5 changes the question

DDR5 restructures the module. Each DDR5 RDIMM is split into two independent sub-channels of 32 data bits each — 40 bits with ECC — so one module already behaves like two narrower channels to the controller. Voltage regulation moved onto the module itself via a PMIC, and the DRAM devices perform on-die ECC internally, which is separate from and additional to the system-level ECC the memory controller runs.

On DDR5 platforms such as Sapphire Rapids (LGA4677, eight channels per socket) and EPYC Genoa (SP5, twelve channels per socket), the highest capacities are generally reached with 3DS RDIMMs rather than classic LRDIMMs. The practical question shifts from RDIMM versus LRDIMM to rank count, 3DS versus non-3DS, and whether leaving channels empty is acceptable for the capacity you need. Newer platforms also introduce MRDIMM, which multiplexes ranks to raise effective throughput, but it is tied to specific CPU families and is not a drop-in for existing DDR5 boards.

Where to go from here

The memory decision is inseparable from the platform decision: channel count, DIMMs per channel and supported module types are all fixed by the socket. Browse the refurbished servers to see which generations match your capacity target, or open Build Your Server to specify CPU, module type, rank and per-channel population yourself and send the configuration over for a quote. If you tell us the workload rather than the part numbers, we will sanity-check the population plan before anything ships.